Mordassa

  Loading movupd xmm0 ... (SSE move unaligned packed double into 128-bit ) vmovaps ymm0 ... (AVX move aligned packed single into 256-bit) Operating –vaddpd ymm1 ymm2 (AVX add packed double 256-bit) –addsd(SSE Add scalar doubles–SSE, but NOT vector op!) KEY – v = AVX – p, s = packed, scalar – u, a = unaligned, aligned – s, d = single, double Source: http://www.cac.cornell.edu/education/training/ParallelFall2012 /Vectorization.pdf

SSE2 16 Byte AVX 32 Bytes Xeon Phi 64 Bytes Alignment increases the efficiency of data loads and stores to and from the processor. When targeting the Intel® Supplemental Streaming Extensions 2 (Intel® SSE 2) platforms, use 16-byte alignment that facilitates the use of SSE-aligned load instructions. When targeting the Intel® Advanced Vector Extensions (Intel® AVX) instruction set, try to align data on a 32-byte boundary. (See Improving Performance by Aligning Data .) For Intel® Xeon Phi™ coprocessors, memory movement is optimal on 64-byte boundaries. (See Data Alignment to Assist Vectorization .) https://software.intel.com/en-us/articles/explicit-vector-programming-best-known-methods

SSE2 16 Byte AVX 32 Bytes Xeon Phi 64 Bytes Alignment increases the efficiency of data loads and stores to and from the processor. When targeting the Intel® Supplemental Streaming Extensions 2 (Intel® SSE 2) platforms, use 16-byte alignment that facilitates the use of SSE-aligned load instructions. When targeting the Intel® Advanced Vector Extensions (Intel® AVX) instruction set, try to align data on a 32-byte boundary. (See Improving Performance by Aligning Data .) For Intel® Xeon Phi™ coprocessors, memory movement is optimal on 64-byte boundaries. (See Data Alignment to Assist Vectorization .) https://software.intel.com/en-us/articles/explicit-vector-programming-best-known-methods