Entrades

Array of pointers in Fortran

In order to have an array of pointers use the following form: type(objectContainer), allocatable :: some(:) ... type objectContainer class(object), pointer :: toObj end type Do not fall into the mistake to use the form below as it is a pointer to an array class(object), pointer :: some(:) nor type(object), pointer :: some(:)

gFortran allocatable arrays and intrinsic all function

Be carefull when using allocatable arrays and all builtin method. The compiler is not able to detect the different sizes. So it provides a false positive when tested with the first value  of the array. Check below an example: program allbug implicit none real, allocatable :: values(:,:) allocate(values(3,1)) values(:, 1) = [26., 27., 28.] write(*,*) "values= ", values write(*,*) "the same vs 26?", all(values(:, 1) == [26.] ) write(*,*) "the same vs 27?", all(values(:, 1) == [27.] ) end program    The output: bash:~/projects$ ./a.out values= 26.0000000 27.0000000 28.0000000 the same vs 26? T <---- HERE! the same vs 27? F On the other hand, when it is done with an explicit array an error is raised at compilation time. all-fixed.f90:10:36-51: 10 | write(*,*) "the same vs 26?", all(values(:, 1) == [26.] ) | 1 2 Error: Shapes for operands at

Memory alignment for multidimensional arrays

Multi-dimensional arrays need to be padded in thefastest-moving dimension, to  ensure array sec9ons to be aligned at the desired byte boundaries : Fortran: first array dimension  C/C++: last array dimension    npadded= ((n +veclen– 1) /veclen) *veclen No alignment requested:veclen= 1 16-byte alignment (SSE):veclen= 4 (sp) or 2 (dp) 32-byte alignment (AVX2):veclen= 8 (sp) or 4 (dp) 64-byte alignment (AVX-512):veclen= 16 (sp) or 8 (dp) Example: real, allocatable:: a(:,:), b(:,:), c(:,:) !dir$ attributes align : 32 :: a,b,c ... allocate (a(npadded,n)) allocate (b(npadded,n)) allocate (c(npadded,n)) ... do j=1,n   do k=1,n     !dir$ vector aligned     do i=1,npadded       c(i,j) = c(i,j) &+ a(i,k) * b(k,j)     end do   end do end do Source

How to reinstall django 1.8 initial database configuration

Deal with the database: sudo su postgresql psql drop database somedatabase; CREATE DATABASE somenewdb OWNER geodjango TEMPLATE template_postgis ENCODING 'utf8'; \q exit export DJANGO_SETTINGS_MODULE='src.settings' Go to your src folder: ./manage makemigrations ./manage migrate ./manage.py loaddata initial-data-fixtures ./manage.py loaddata initial-data-consulta

Papi_avail for SandyBridge E5-2680

Available PAPI preset and user defined events plus hardware information. -------------------------------------------------------------------------------- PAPI Version             : 5.4.1.0 Vendor string and code   : GenuineIntel (1) Model string and code    : Intel(R) Xeon(R) CPU E5-2680 0 @ 2.70GHz (45) CPU Revision             : 6.000000 CPUID Info               : Family: 6  Model: 45  Stepping: 6 CPU Max Megahertz        : 2700 CPU Min Megahertz        : 1200 Hdw Threads per core     : 2 Cores per Socket         : 8 Sockets                  : 2 NUMA Nodes               : 2 CPUs per Node            : 16 Total CPUs               : 32 Running in a VM          : no Number Hardware Counters : 11 Max Multiplex Counters   : 32 -------------------------------------------------------------------------------- ================================================================================   PAPI Preset Events ================================================================================    

Intel Basic assembly notation SIMD

  Loading movupd xmm0 ... (SSE move unaligned packed double into 128-bit ) vmovaps ymm0 ... (AVX move aligned packed single into 256-bit) Operating –vaddpd ymm1 ymm2 (AVX add packed double 256-bit) –addsd(SSE Add scalar doubles–SSE, but NOT vector op!) KEY – v = AVX – p, s = packed, scalar – u, a = unaligned, aligned – s, d = single, double Source: http://www.cac.cornell.edu/education/training/ParallelFall2012 /Vectorization.pdf

Intel Data Alignment

SSE2 16 Byte AVX 32 Bytes Xeon Phi 64 Bytes Alignment increases the efficiency of data loads and stores to and from the processor. When targeting the Intel® Supplemental Streaming Extensions 2 (Intel® SSE 2) platforms, use 16-byte alignment that facilitates the use of SSE-aligned load instructions. When targeting the Intel® Advanced Vector Extensions (Intel® AVX) instruction set, try to align data on a 32-byte boundary. (See Improving Performance by Aligning Data .) For Intel® Xeon Phi™ coprocessors, memory movement is optimal on 64-byte boundaries. (See Data Alignment to Assist Vectorization .) https://software.intel.com/en-us/articles/explicit-vector-programming-best-known-methods